KHB: Synthesis: An Efficient Implementation of Fundamental Operating Systems Services

Any concurrency primitive for shared-memory multiprocessors on commodity hardware must for performance reasons be implemented at the cache-coherency level, using message passing (rather than having to hit the underlying slow, shared RAM on every synchronous operation) and is therefore several orders of magnitude more complex in silicon than anything that can be done "with 1 bit".

See http://lwn.net/Articles/252125/ (scroll down to section 3.3.4, Multi-processor support).

CAS and the spicier double-word CAS are obviously 'trickier' in some sense than LL/SC but both must be implemented by grabbing exclusive access over a cache line (maybe two in the case of double-word, I suppose). The underlying mechanics are the same.