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Observations on power managementObservations on power managementPosted Nov 25, 2008 0:40 UTC (Tue) by JoeBuck (subscriber, #2330)In reply to: Observations on power management by alecs1 Parent article: Observations on power management Your formula describes dynamic power from CMOS switching, assuming that everything operates on the same clock. However, these days leakage power is a major issue and can be as large as dynamic power. Since leakage power (roughly speaking) is linear in the voltage and isn't affected by the clock frequency, and since leakage power can be turned off by turning major hunks of the chip off, this tends to make it more effective to "race to idle" and turn the chip off than to voltage-scale. For some small embedded RISC processors the tradeoffs are different.
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