I think this has already been discussed here, but making the frequency go down can bring smaller voltages, and Matthew Garrett seems to be aware of it.
Wikipedia on SpeedStep:
"P = C(V^2)f
[...] For example, for a 1.6 GHz Pentium M, the clock frequency can be stepped in 200 MHz increments over the range from 1.6 to 0.6 GHz. At the same time, the voltage requirement decreases from 1.484 V to 0.956 V. The result is that the power consumption theoretically goes down by a factor 6.4.".
The article goes on an aknoledges that this is only a teoretical computation.
Also, running at smaller frequencies may prevent the fans from spinning up, but I don't know how important that is.
Until I see benchmarks, I can't fully trust these CPU claims.
Posted Nov 25, 2008 0:40 UTC (Tue) by JoeBuck (subscriber, #2330)
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Your formula describes dynamic power from CMOS switching, assuming that everything operates on the same clock. However, these days leakage power is a major issue and can be as large as dynamic power.
Since leakage power (roughly speaking) is linear in the voltage and isn't affected by the clock frequency, and since leakage power can be turned off by turning major hunks of the chip off, this tends to make it more effective to "race to idle" and turn the chip off than to voltage-scale. For some small embedded RISC processors the tradeoffs are different.
Wrong CPU!
Posted Nov 25, 2008 11:30 UTC (Tue) by niner (subscriber, #26151)
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What you describe is SpeedStep, which is available in Pentium M and Core CPUs. The
article talked about p4-clockmod, which handles Pentium 4 and Pentium 4-M CPUs,
which _do not_ alter the voltages.