Getting a handle on caching [LWN.net]

Getting a handle on caching

Posted May 20, 2008 22:20 UTC (Tue) by arjan (subscriber, #36785)
In reply to: Getting a handle on caching by giraffedata
Parent article: Getting a handle on caching

The weakness of MTRR is that there are only 7 or 8 of them.
And a whole bunch are initially set up by the bios (usually 6 or 7, sometimes more)..... and
those are both needed and untouchable.
(while you *can* change them, it then breaks SMM mode and suspend/resume etc etc)

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Getting a handle on caching

Posted May 21, 2008 2:40 UTC (Wed) by giraffedata (subscriber, #1954) [Link]

The weakness of MTRR is that there are only 7 or 8 of them. And a whole bunch are initially set up by the bios (usually 6 or 7, sometimes more)..... and those are both needed and untouchable.

Again, it's confusing to say that the fact some are initially set up by the BIOS is a problem. The fact that they're needed and untouchable is the problem, and it would be regardless of who set them up. So if you really want to explain why MTRRs are in short supply, you have to give an idea of what those 6 or 7 are for.

Are SMM mode and suspend/resume etc. etc. BIOS functions? If so, I guess the clear way to say it is that a whole bunch are used by the BIOS.

BTW, I found on my system, I had to free up some MTRRs by combining ranges, making a few more uncacheable pages than there would ideally be. A big reason all 8 were used is that each one must cover a power of two size block of memory, so it takes 5 registers to describe 31 pages of memory, but only one register to describe 32 pages.