Getting a handle on caching

MTRRs can be setup in an overlapping mode where UC MTRRs trump WB MTRRs.
In that case even if there are spare MTRRs the only way we can get WC
memory regions is to through the use of PAT.

BIOS's do that even on Boxes where it isn't strictly necessary to
avoid going over the 8 MTRR limit.

Other details.

WC (write combining) technically allows read combining as well.
Just none of the current instructions take advantage of that fact.

Where PAT really wins is if you have a several high performance
cards in your system that want to take advantage of WC.  Which
they can't do today because of the limitation in PAT resources.

WC when the hardware takes advantage of it can be a real performance win.
In one extreme example I saw a specialized low latency network card generate line rate 8Gpbs
traffic directly from the cpu without touching
memory.  So it is very nice when you can get it.

Eric