Matthew Garrett on the race to idle

Matthew Garrett on the race to idle

Posted May 9, 2008 18:13 UTC (Fri) by JoeBuck (subscriber, #2330)
Parent article: Matthew Garrett on the race to idle

I think Matthew might be oversimplifying. The real issue is whether, on a given processor, halving the clock frequency saves more than half the power, or less than half the power.

The dynamic power consumed by a CMOS circuit is proportional to the square of the voltage, while the clock speed is proportional to the voltage itself. Leakage power is constant. So, at least for embedded processors, like ARMs, where leakage power is low, voltage scaling can be a win over sleeping: you halve the speed and power drops by nearly a factor of four.

For 65 nm or 45 nm silicon, leakage power is considerable, and the only way to get rid of it is to sleep. Also, noise margins might not allow all voltages to be scaled very much. So it might well be that, for a given processor, voltage scaling always loses as compared to sleeping. But it certainly isn't true in most cases for embedded systems under a predictable load (doing DSP applications like video encoding/decoding or CDMA/GSM modem operation).

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Yeah, I should probably have made it clear that I'm primarily talking about x86 here. Things
are likely to be different in the embedded world, especially given the different constraints
that system on chip designs tend to impose on you.

You still have to allow for the fact that the rest of the system (disk drive, display) is
still drawing power.  It's like speeding up a small section of code by a factor of ten -- if
that code only runs 10% of the time, you have only speeded up the entire program by 9% (isn't
this Amdahl's law?).  Factoring in just the CPU power doesn't answer the question properly.
You may end up using more power and drawing down your battery even further.

In fact, TFA said this.

> Leakage power is constant.

Should it be proportional to voltage?

It's been many years since I've done VLSI but, yes, we normally modeled leakage as a constant.
It's mostly affected by temperature and process characteristics, not voltage.

If applied voltage is near the thermal voltage (25.9mV) then I suppose you might have to
include voltage in the equation.  But we're nowhere near that today and I'm not sure anyone
would ever want to run that close to the noise floor (I know, I know, 640K should be enough
for anybody...  we'll see!)

> we normally modeled leakage as a constant.

My understanding is that leakage *current* is nearly constant (unless the voltage difference
is very small), so leakage power is proportional to voltage, and leakage energy is
proportional to voltage multiplied by time, i.e., voltage divides by frequency.  Since voltage
divides by frequency is increases not very much when you decrease frequency, this is nearly
constant energy.  If leakage *power* is constant instead, the leakage energy will be
proportional to the inverse of frequency.  Then voltage scaling would be doing something very
bad to energy consumption!

Would you mind clarifying what do you mean by "original power saving equation" and "dubious"?

Um, except that chips like ARMs are hyper-optimised for sleep, and most (I'm excluding
insanity like StrongARM here) consume an absolute crapteenth of what they do running, while
asleep? It's not even really so much a race to idle, as a race to sleep, or even retention.