True. Lightspeed means that at 1Ghz, no signal can travel more than about 30cm. At 3Ghz, no
signal can travel more than 10cm. And switching-times aren't instantaneous, so the practical
limits on die-size are smaller.
I'd like to point out though, that the *physical* limit on serially dependant computation is a
*volume* and not an *area*.
If lightspeed allows a 100mm^2 (10mm by 10mm) then lightspeed also allows a cube of 10mm by
10mm by 10mm, or 1000mm^3.
There are reasons we don't do it that way, both construction and cooling would be a real
bitch. It's hard enough dealing with the multiple layers we have on todays CPUs, making an
awful LOT more layers would -not- simplify design.
Posted Apr 28, 2008 11:34 UTC (Mon) by khim (subscriber, #9252)
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It's hard enough dealing with the multiple layers we have on todays CPUs, making an awful LOT more layers would -not- simplify design.
Before we'll do this we'll need technology for at least two layers. Currently we are using one and only one transistor-layer in our CPUs. Sure there are talks about 7, 9 even 15 layers - but these are metalization layers - all transistors (which do actual work) are in single layer...
You can easily glue many dies together - but again, it's multicores, not bigger hot-spot...
Volume? Not yet...
Posted Apr 28, 2008 11:56 UTC (Mon) by ekj (subscriber, #1524)
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True.
My point was just that if you're only concerned with PHYSICAL limitations, like lightspeed,
then the limit is a volume, and not an area.
I agree with you we are nowhere near being technically capable of designing and manufacturing
a true 3d cpu (one that uses the entire volume of say a 1000mm3 to do computation)
But this is a technical limitation, and one that can, atleast in principle, be overcome. And
not a physical one that asfar as we know is final -- like lightspeed.