Short subjects: kerneloops, read-mostly, and port 80 [LWN.net]

Short subjects: kerneloops, read-mostly, and port 80

Posted Dec 20, 2007 20:01 UTC (Thu) by im14u2c (subscriber, #5246)
Parent article: Short subjects: kerneloops, read-mostly, and port 80

What happens if you mark "write often" variables as having an alignment equal to the L2 line
size?  That'd force them into separate cache lines, and other stuff with lesser alignment
constraints could still fill in the holes.  (This works for scalars at least, if not arrays.)

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Short subjects: kerneloops, read-mostly, and port 80

Posted Dec 20, 2007 20:08 UTC (Thu) by im14u2c (subscriber, #5246) [Link]

Also, it occurs to me that even this strategy might be a bad one, since you still have the
problem of reads to unrelated variables causing some amount of cache line traffic for
writeable lines.  Furthermore, the "best" strategy may vary by processor.

How many "write often" variables are there that are not per-CPU?  If this set is moderately
small, perhaps forcing them all into separate cache lines with *nothing* in the holes is an
acceptable increase in footprint in modern CPUs.  And, on AMD CPUs, you may be able to skip
this altogether:  The MOESI cache protocol they use allows cache lines to be in a "shared,
writeable" state (the "O" state), which directly addresses this bounce issue.