Definition of "cache coherency"
Posted Nov 24, 2007 10:37 UTC (Sat) by ncm
Parent article: "What every programmer should know about memory" - the PDF version
A fundamental error found on page 16 remains.
The erroneous text is, "In symmetric multi-processor (SMP) systems
the caches of the CPUs cannot work independently from each other.
All processors are supposed to see the same memory content at all
times. The maintenance of this uniform view of memory is called
'cache coherency'." (Emphasis added.)
There are two errors here. First, it is not true that on all SMP
systems, all processors are supposed to see the same memory content
at all times. It is normal, e.g. on SMP PPC and Itanium
systems, for different CPUs to see different values at the same
address for some time after a write operation by one CPU, unless
"barrier instructions" have been run after the write operation
on both the writing and reading processors. The second error is
related: the text above is not a correct definition of "cache
coherency" as used by modern computer architects. Cache coherency
requires that all processors eventually see writes by others
(e.g., after the barrier instructions), not that they see the effect
of all writes immediately.
The x86 architecture definition provides guarantees to the
programmer about when writes by one processor are visible to
others without barrier instructions, but these
guarantees make the cache architecture much more complex, and
less able to scale efficiently to more than a few processors.
This complexity also makes it just that much less likely that the
cache system will actually have been implemented correctly in
every case. Unfortunately, buggy hardware remains in service
long after the bug is known, making these "guarantees", and code
that depends on them, less reliable.
(If these turn out to be the only serious errors in the document,
it would remain a remarkable achievement.)
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