Posted Nov 22, 2007 22:38 UTC (Thu) by anton
Parent article: Memory part 8: Future technologies
FB-DRAM has already been deployed for quite some time in current
multi-socket Xeon systems, and IIRC also in Niagara-based Suns.
However, the high power consumption and heat dissipation of FB-DIMMs
leads Intel to also provide Dual-Xeon chipsets that support plain
registered DIMMs; unfortunately, the higher pin count of the regular
DDR2 interface mean that this chipset supports only two channels
instead of four. AMD still has an advantage here (two DDR2 channels
Concerning Cell SPUs and memory latency: the SPUs can only access
their local memory (256KB), not the main memory. If data or code
needs to be loaded into the local memory, software has to program the
transfer from main memory explicitly (unlike cache, which is
automatic). So, yes, explicit prefetching is necessary, otherwise the
SPU won't get it's data at all.
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