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Memory part 7: Memory performance toolsMemory part 7: Memory performance toolsPosted Nov 7, 2007 17:01 UTC (Wed) by james (subscriber, #1325)Parent article: Memory part 7: Memory performance tools
...since an L1d miss implies, for Intel processors, an L2 miss...Presumably the other way round (L2 miss implies L1 miss).
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Memory part 7: Memory performance tools Posted Nov 8, 2007 17:13 UTC (Thu) by mebrown (subscriber, #7960) [Link] Actually, since Intel processors use an inclusive cache, the original statement is correct. If it isnt in L1, it isnt in L2, either, since L2 includes all the contents of L1.
L1/L2 Posted Nov 8, 2007 17:22 UTC (Thu) by corbet (editor, #1) [Link] Actually, since Intel processors use an inclusive cache, the original statement is correct. If it isnt in L1, it isnt in L2, either, since L2 includes all the contents of L1. L2 contains everything in L1, but, since it's larger, it contains data which is not in L1 as well. If L2 cannot satisfy an occasional L1 cache miss, why does it exist? I have a question into Ulrich on how he really wanted this paragraph to read, stay tuned.
L1/L2 Posted Nov 8, 2007 17:31 UTC (Thu) by mebrown (subscriber, #7960) [Link] Right. Doh. In my defense, I had not actually drank any of my coffee before posting that comment.
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