Various topics, all related to interrupts

Actually, the "what every programmer should know about memory series" <i>hasn't</i> described,
in detail, issues of modern processors' reordering of memory operations to avoid pipeline
stalls. Thus far, we have half-truths like, "All processors are supposed to see the same
memory content <i>at all times</i>. The maintenance of this uniform view of memory is called
'cache coherency'”.  (My emphasis)

I hope the series will come clean about what cache coherency really means, and what it takes,
in general, for two processors to "see the same memory content", and when one can hope they
will.