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Should disclose: x86 specificShould disclose: x86 specificPosted Oct 3, 2007 1:14 UTC (Wed) by mikov (subscriber, #33179)In reply to: Should disclose: x86 specific by ncm Parent article: Memory part 2: CPU caches
I think that you may be confusing cache coherency with memory consistency. Although they are obviously related, in the context of the article the latter is not important.
To the best of my knowledge, the description in the article applies to all cache coherent systems, including the ones listed in your previous post. It has nothing to do with memory consistency, which is an issue mostly internal to the CPU.
I am very possibly wrong, of course - I am not a hardware system designer - so I am glad to discuss it. Can you describe how the cache/memory behavior in an Alpha (for example; or any other weak consistency system) differs from the article ?
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Should disclose: x86 specific Posted Oct 3, 2007 1:48 UTC (Wed) by ncm (subscriber, #165) [Link] I'm sorry, I should have pointed out this quote from the article: "All processors are supposed to see the same memory content at all times.". (My emphasis.)I agree that coding with memory barriers (etc.!) is a big subject, and beyond the scope of this installment. It would have sufficed, though, to mention that (and where) it is a matter for concern, and why.
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