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Reader CommentsReader CommentsPosted Sep 26, 2007 23:25 UTC (Wed) by drepper (subscriber, #5153)Parent article: What every programmer should know about memory, Part 1
I appreciate (most of) the comments and actually made already a few changes based on them to clarify a few things (and correct typos etc).
But I'm not going to reply to anything specific here and now. This is just section 2 (with 1 only being an introduction). Some of what has been discussed in comments goes far beyond what is in these sections. Once you've read section 6 you probably have a better understanding about what is covered and what isn't (and to some extend: why certain things are covered in the first place).
So, don't regard my silence as a sign of disinterest, it just means that many questions will automatically be answered later.
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Reader Comments Posted Oct 1, 2007 22:22 UTC (Mon) by roelofs (guest, #2599) [Link] Two more clarification-comments:Recent RAM types require two separate buses (or channels as they are called for DDR2, see Figure 2.8) which doubles the available bandwidth. Unless I'm missing something fundamental, Figure 2.8 has nothing to do with DDR2 channels. Indeed, I don't believe the comment even refers to Figures 2.12 or 2.13; I see nothing relevant. Perhaps the figure in question was dropped at some point? In this example the SDRAM spits out one word per cycle. Here and in several other places, the text is ambiguous. "Cycle" in this context apparently means clock cycle, but there's an implicit (larger) cycle measured from RAS to RAS (for example) that defines the overall throughput. Figure 2.8 actually shows four words going out in that larger cycle. Greg
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