| |||||||||||||
Bridges connected to each other through FSBBridges connected to each other through FSBPosted Sep 24, 2007 16:17 UTC (Mon) by giraffedata (subscriber, #1954)In reply to: What every programmer should know about memory, Part 1 by tyhik Parent article: What every programmer should know about memory, Part 1
AFAIK the bridges are not connected to each other through FSB. And at the top of the article, it basically says that (and shows it in a drawing). A similar contention question left open is that of contention in the Northbridge. Can that be a bottleneck? And what is it for, anyway? One could imagine the memory controller being directly on the FSB.
(Log in to post comments)
Bridges connected to each other through FSB Posted Sep 26, 2007 18:20 UTC (Wed) by csnook (guest, #36935) [Link] The northbridge is the barrier between the CPU domain (FSB, HT, etc.), which has to deal with cache coherency, locking, interrupt delivery, etc. and the rest of the system, which simply passes serial messages or parallel data/address tuples around. On a sufficiently primitive system you don't really need one, but all modern commodity microarchitectures have something like a northbridge either on the chipset or the processor itself.
As for bottlenecks, even if the northbridge itself has enough internal bandwidth between all of its ports to function in a non-blocking fashion, you can't have a bottleneck-free network unless both the CPU and the I/O controllers have dedicated bandwidth to the memory. That only makes sense with multi-port DRAM, which isn't used for main memory in any commodity system.
|
|||||||||||||