Posted Sep 11, 2007 18:54 UTC (Tue) by Nick
In reply to: KS2007: Scalability
Parent article: KS2007: Scalability
It was tricky to get into exact details of what was happening here.
One issue is data going over the interconnect on NUMA systems -- in
this case, obviously you cannot avoid actually sending the page
data over RAM. Basically we really have to make sure userspace does
the right thing.
Another issue is from which CPU should you do the pagecache writeout
from. And in this case you do want to do it on the same node that
most of the pages are located on (rather than where the device is,
because it's a question of which would require touching more data
For the problem you describe, it is different again. And yours does not
apply only to NUMA but also SMP. And basically I gather what you are
doing is trying to hand over control of the block layer to the completing
CPU at a point that is going to result in the fewest cache misses. We
didn't really discuss this in detail, but yes some of the points that
were raised included the upcoming hardware, and also the fact that network
might have similar concerns, and it might be good to work on them together.
I still hope to see continued work on your ideas, and I don't think they
were shot down at all (if I remember correctly).
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