| |||||||||||||
Why add anything?Why add anything?Posted Apr 5, 2007 18:57 UTC (Thu) by joib (guest, #8541)In reply to: Why add anything? by ncm Parent article: Application-friendly kernel interfaces
One problem is that the number of large page TLB entries is quite limited. E.g. on current Opterons, while you have a 512-entry data TLB for the normal 4K pages, for the 2M large pages you only have 8 entries. So if you have a loop kernel reading/writing from more than 8 big arrays you're going to have TLB trashing.
I would presume that for non-HPC applications these non-streaming, irregular access patterns are even more common. Though supposedly AMD is fixing this issue with the upcoming 'Barcelona' by having 128 2M TLB entries, and additionally supporting 1G pages (don't know how many TLB entries for those).
For comparison, the Intel Woodcrest has 256 4K and 32(?) 2M TLB entries.
(Log in to post comments)
|
|||||||||||||