| |||||||||||||
Remember the iAPX 432?Remember the iAPX 432?Posted Jan 18, 2007 5:38 UTC (Thu) by BrucePerens (guest, #2510)Parent article: LCA: Andrew Tanenbaum on creating reliable systems The iAPX 432 was an Intel CPU designed to run Ada reliably. It used a message-passing paradigm for communication between functions, and every function ran in its own privilege ring. So, a single function, rather than an entire microkernel, could protect itself from the rest of the system. At the time (around 1980) it took 4 PC boards to implement the CPU, and ran slow as molasses. It could be implemented within a single chip today, and would run at a reasonable speed. Why isn't anyone working on this? There are lots of applications that could use it. Bruce
(Log in to post comments)
Remember the iAPX 432? Posted Jan 18, 2007 6:57 UTC (Thu) by drag (subscriber, #31333) [Link] Lisp machines redux?
Remember the iAPX 432? Posted Jan 18, 2007 16:26 UTC (Thu) by AJWM (guest, #15888) [Link] Kind of.
The iAPX 432 was (as I recall) designed to be an Ada machine in the same way that e.g. the Burroughs B6700 et al were designed to be Algol machines (or Algol & Cobol machines). (Actually I think the 432 started out as a more generic HLL machine but when DOD finalized on Ada, Intel made the obvious moves to accomodate.)
Remember the iAPX 432? Posted Jan 20, 2007 0:43 UTC (Sat) by brouhaha (subscriber, #1698) [Link] That's correct. Ada was only in a very early stage of development when the 432 project started (originally as the 8800), and was not the target at that time. The first language to ship for the 432 was actually a dialect of Smalltalk.
The 432 architecture was very similar in concept, if not in detail, to the JVM.
Remember the iAPX 432? Posted Jan 20, 2007 11:03 UTC (Sat) by drag (subscriber, #31333) [Link] Well you have the 'Open Graphics' project recently got their first prototype board. It's all re-programmable and all that.
They have pictures and specifications at:
Also HP has their new innovations with their FPGA designs were it allows faster speeds and much less waste of die space compared to older FPGA technology...
And you have Sun GPL'ng their cpu design, which is interesting (if currently a bit pointless).
And now you have Sun with their open source JVM.
Now I am a bit ignorant, and I know that there is a huge difference between programming for C vs programming a FPGA or whatnot, but what is the posibility for using a programmable proccessor for running, or at least accelerating, a Java Virtual Machine?
Or maybe a simplified Lisp environment?
Would it be worth it for a certain group of people to have hardware specificly tailored for a paticular software programming language?
Remember the iAPX 432? Posted Jan 18, 2007 7:03 UTC (Thu) by eru (subscriber, #2753) [Link] You could do a lot of that by using a regular Intel 32-bit x86 architecture chip the way the original designers of its security features apparently intended: Put almost everything in its own segment, use the 4 rings to give least privilege to code modules, use call gates, etc.And you get quite a performance hit over the "unixy" way of using it. But it could be a lot more secure.
Remember the iAPX 432? Posted Jan 18, 2007 22:27 UTC (Thu) by JoeBuck (subscriber, #2330) [Link] I've met the former Intel exec who was in charge of the 432. The 432 is a great example of an interesting failure, interesting because of how much it taught people and the influence that it had on the industry. It certainly influenced David Patterson, father of RISC (and no, the x86 didn't really defeat RISC, since all modern x86 machines are RISC internally, with the CISC instructions translated to RISC micro-ops on the fly).The idea of the 432 was to close the semantic gap, by directly supporting high-level language constructs in hardware. The VAX architecture had similar ideas, though the VAX didn't take things as far. The problem is that you pay through the nose for this stuff, and there's no way to avoid the penalty, even in cases where the compiler can easily prove that the condition the hardware is protecting against can't happen. Complex microcode is needed to handle all the possible corner-cases. The end result is that even though the hardware has specialized stuff to handle the complex language constructs, much simpler hardware beat the pants off of heavyweight monstrosities, with vastly less silicon area and power.
|
|||||||||||||