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Counting on the time stamp counterCounting on the time stamp counterPosted Nov 16, 2006 3:23 UTC (Thu) by jreiser (subscriber, #11027)Parent article: Counting on the time stamp counter The TSC can also be read quickly (it is just a CPU register, after all) ... This theory has never been correct for x86 processors. The minimum cost for rdtsc was 9 cycles in a PentiumMMX-166MHz. On a Pentium4Xeon-3.0GHz it takes 97 cycles. The conclusion? The hardware reads TSC serially one bit at a time, or one byte at a time on old processors.
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Counting on the time stamp counter Posted Nov 16, 2006 4:41 UTC (Thu) by PaulMcKenney (subscriber, #9624) [Link] The rumor I hear is that reading TSC does some degree of instruction-stream serialization. Someone from Intel or AMD might be able to shed better light on the performance of rdtsc.
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