ts7300_opencore 1.0 announced [LWN.net]

The OpenCollector site has an announcement for a new Verilog project for the Technologic Systems TS-7300 FPGA Computer. "Intended as a boilerplate for future open-source FPGA designs using this hardware, it includes WISHBONE bus demultiplexing logic as well as a reference implementation of the open-source ethernet core at http://www.opencores.org. Also included is sample WISHBONE stub logic exhibiting the minimal HDL required to implement a single WISHBONE 32-bit register controlling LEDs in the address space of the EP9302 200Mhz ARM9 processor running Linux 2.4."

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