| |||||||||||||
per-CPU counters and lockingper-CPU counters and lockingPosted Feb 9, 2006 4:57 UTC (Thu) by roelofs (guest, #2599)In reply to: per-CPU counters and locking by giraffedata Parent article: The search for fast, scalable counters Now, there are 4 levels of electronic memory (including the registers) 5 levels sometimes (at least in principle). There exist Intel chips with L3 caches (Xeon Gallatin, I think), and presumably each cache type is a different speed from the others and from main memory. Greg
(Log in to post comments)
|
|||||||||||||