per-CPU counters and locking
Posted Feb 9, 2006 4:57 UTC (Thu) by roelofs
In reply to: per-CPU counters and locking
Parent article: The search for fast, scalable counters
Now, there are 4 levels of electronic memory (including the registers)
5 levels sometimes (at least in principle). There exist Intel chips with L3 caches (Xeon Gallatin, I think), and presumably each cache type is a different speed from the others and from main memory.
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