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per-CPU counters and lockingper-CPU counters and lockingPosted Feb 5, 2006 0:35 UTC (Sun) by giraffedata (subscriber, #1954)In reply to: Mean value by madscientist Parent article: The search for fast, scalable counters Who said anything about semaphores with per-CPU counters? The article specifically said there is no locking required for updating a per-CPU counter. It says you never read a per-CPU counter. Also, there is no locking required to read the global counter. Now as for the orthogonal issue of getting a complete count instead of just reading the global counter: how are you going to read the per-CPU counter of another CPU? The only way is for that CPU to write it out to main memory and for you to go to main memory to get it. That takes a long time, and that's the slowness that per-CPU counters are supposed to eliminate.
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per-CPU counters and locking Posted Feb 5, 2006 2:11 UTC (Sun) by man_ls (subscriber, #15091) [Link] how are you going to read the per-CPU counter of another CPU?Never thought of that; just another example of why kernel programming sometimes looks so hard to outsiders. The only way is for that CPU to write it out to main memory and for you to go to main memory to get it. That takes a long time, and that's the slowness that per-CPU counters are supposed to eliminate.At least it would spare the "expensive locking operations" mentioned in the main article, wouldn't it?
per-CPU counters and locking Posted Feb 5, 2006 3:13 UTC (Sun) by giraffedata (subscriber, #1954) [Link] just another example of why kernel programming sometimes looks so hard to outsiders. This is a relatively recent addition to the things performance programmers have to worry about. Used to be, electronic memory was considered fast, and it was always the same speed. Typically, it took at most 4 cycles to access it. Now, there are 4 levels of electronic memory (including the registers) and the main pool is 200 cycles away. We think of looking at memory now the way we used to think of loading a file from a disk. I'm not ashamed to say my personal leaning these days is toward single-CPU single-core machines tied together at the network adapter. My brain can handle only so much complexity.
At least it would spare the "expensive locking operations" mentioned in the main article, wouldn't it? That locking operation is for updating a counter. For accessing one, the only cost is moving the cache line from one CPU to another -- through main memory. Whoops, I just remembered - on fancy modern machines, there's a shortcut to move a cache line without going out on the memory bus. So it's cheaper than what I said earlier, but still more than folks are willing to pay.
per-CPU counters and locking Posted Feb 9, 2006 4:57 UTC (Thu) by roelofs (subscriber, #2599) [Link] Now, there are 4 levels of electronic memory (including the registers)5 levels sometimes (at least in principle). There exist Intel chips with L3 caches (Xeon Gallatin, I think), and presumably each cache type is a different speed from the others and from main memory. Greg
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