Version 20060109 of Covered
a Verilog code coverage analysis tool, is available.
"It has been almost a year since the last development release of Covered, but in the meantime there has been a lot of work put into the score command of Covered during this time to fix bugs, add more coverage support for various Verilog constructs, simulate more accurately, remove memory corruption/estrangement and improve the run-time speed of the score command. I think that user's of Covered will appreciate the enhancements. Documentation updates have been made and build problems have been fixed (Covered now compiles cleanly for Fedora Core 3 builds).
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