Kernel Summit 2005: The processor panel

From LWN's 2005 Kernel Summit coverage.

The 2005 kernel summit started off with the now-traditional CPU architects' panel, where representatives from various processor manufacturers are invited to share their plans - if not their marketing slides - with the developers.

First up this year was Michael Day from IBM, who gave an overview of the cell processor architecture. There was not much in this presentation which goes beyond the publicly available information. Cell looks like a nice processor for many applications, especially those requiring high graphics or single-precision floating point performance. This processor still seems driven by its initial Playstation deployment, with other applications to be addressed later on.

Per Hammarlund represented Intel; he is a Pentium 4 designer with specific responsibility for the hyperthreading features.

Intel's plans for the x86 family include going to a dual-core architecture across the entire product line. The processors will also move to common internal core, based on the mobile processors. When asked, Per confirmed that this change is being driven by power management concerns. He noted that Intel is able to build processors with some fairly heavy power requirements, and that even large server systems have power management issues.

In fact, power management was the most commonly-heard theme in Per's session. He noted that the developers may want to think a bit more on how they do scheduling for multi-core processors. Scheduling for maximum performance works quite well in Linux; the scheduler distributes tasks across the packages as it should. If, however, your goal is minimal power usage, the best scheduling decisions will be different. Often, the system may want to power down one or more cores, rather than trying to keep all cores busy.

In return, the developers had one request: provide a reliable way to find out how much power the system is actually using. According to Linus, when power consumption can be measured, it will be possible to work on power-aware algorithms and actually benchmark the results. Until then, there will be limits to how much developers will be able to care about power consumption.

It is routine, at events like this, to bug the Intel representatives about the lack of an I/O memory management unit in the x86 processor line. When asked whether Intel would remedy that situation soon, Per suggested that the discussion should be "taken offline." He did, however, mention that future processors will include "DMA engines," but did not get into details.

The final presenter was AMD's Richard Brunner, who has become a regular figure at the kernel summit. He talked mostly about new features to expect in upcoming processor releases. Much of the usual stuff is happening, such as a steady move to smaller-scale chip features; among other things, smaller scale leads to lower power consumption.

AMD expects to unveil a number of virtualization features in 2006. In particular, AMD processors will feature "nested page tables." Nesting appears to be a mechanism which forces virtualized clients to go through the page lookup process twice; the first time through yields an address in the host's virtual space, which is then translated again to get the physical address. This approach can be fast because the translation buffer (TLB), which caches these lookups, will hold the final result. AMD's TLB includes an address space identifier, so each clients cached results can be maintained without having to flush the TLB when going from one client to the next.

Looking further ahead, AMD plans to offer multi-core (meaning "greater than two cores") processors with an L3 cache shared between them. The processors will work with a 48-bit physical address space, and will be able to handle individual pages up to 1GB in size. There will also be a timestamp counter which continues to count at the same rate regardless of the processor's current clock speed; this announcement drew some applause from the audience.

---

(Log in to post comments)